d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct11 triple 3-input and gate for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation triple 3-input and gate 74hc/hct11 features output capability: standard i cc category: ssi general description the 74hc/hct11 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct11 provide the 3-input and function. quick reference data gnd = 0 v; t amb = 25 c; t r = t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d = c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz c l = output load capacitance in pf v cc = supply voltage in v ? (c l v cc 2 f o ) = sum of outputs 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl / t plh propagation delay na, nb, nc to ny c l = 15 pf; v cc = 5 v 10 11 ns c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per gate notes 1 and 2 18 20 pf
december 1990 3 philips semiconductors product speci?cation triple 3-input and gate 74hc/hct11 pin description pin no. symbol name and function 1, 3, 9 1a to 3a data inputs 2, 4, 10 1b to 3b data inputs 7 gnd ground (0 v) 12, 6, 8 1y to 3y data outputs 13, 5, 11 1c to 3c data inputs 14 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol. fig.4 functional diagram. fig.5 logic diagram (one gate). function table notes 1. h = high voltage level l = low voltage level inputs output na nb nc ny lll l llh l lhl l lhh l hll l hlh l hhl l hhh h
december 1990 4 philips semiconductors product speci?cation triple 3-input and gate 74hc/hct11 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: ssi ac characteristics for 74hc gnd = 0 v; t r = t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay na, nb, nc to ny 32 100 125 150 ns 2.0 fig.6 12 20 25 30 4.5 10 17 21 26 6.0 t thl / t tlh output transition times 19 75 95 110 ns 2.0 fig.6 7151922 4.5 6131619 6.0
december 1990 5 philips semiconductors product speci?cation triple 3-input and gate 74hc/hct11 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: ssi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. ac characteristics for 74hct gnd = 0 v; t r = t f = 6 ns; c l = 50 pf ac waveforms package outlines see 74hc/hct/hcu/hcmos logic package outlines . input unit load coefficient na, nb, nc 1.00 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay na, nb, nc to ny 16 24 30 36 ns 4.5 fig.6 t thl / t tlh output transition times 7 15 19 22 ns 4.5 fig.6 fig.6 waveforms showing the input (na, nb, nc) to output (ny) propagation delays and the output transition times. (1) hc : v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v.
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